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PLECS Processor-In-Loop (PIL)

Develop, test, and validate embedded code

Engineers often wish to test their code by executing it inside a circuit simulator when developing embedded control algorithms.

With the PLECS PIL package, this can be done by tying actual code executing on real hardware into the virtual world of a PLECS model.

Instead of reading the physical sensors, values calculated by the simulation tool are used as inputs to the embedded algorithm. Similarly, outputs of the control algorithms executing on the processor are fed back into the simulation to drive the virtual environment.

This approach can expose platform-specific software defects such as overflow conditions and casting errors. PIL simulations can also detect and analyze potential problems related to the multi-threaded execution of control algorithms, including jitter and resource corruption.


A specialized PIL Block is the interface between the simulation model and the embedded processor. We also provide a collection of high-fidelity peripheral models to accurately model the behavior of advanced MCU peripherals such as ADC, PWM, and Capture modules.

Embedded Framework

The PLECS PIL package includes PIL Framework libraries with support for embedded processor families used in power conversion applications. Several communication interfaces are supported by the frameworks and by PLECS to link the processor with the circuit simulator efficiently.

Supported Embedded Processors

Currently, the PLECS PIL package offers support for the following MCUs :

  • TI C2000 Family (including the latest Delfino dual-core processors)

  • ST STM32F4 Series

  • Microchip dsPIC33F (MC version)

For more details, please refer to this link:


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