The PLECS HIL (RT Box) is a state of the art real-time simulator. With its 32 analog and 64 digital input/output channels and its 1 GHz dual-core CPU it is a versatile processing unit for both real-time hardware-in-the-loop (HIL) testing and rapid control prototyping.
At the heart of the RT Box operates a Xilinx Zynq system-on-chip that consists of an FPGA and 2 CPU cores. The tight integration between the FPGA and CPU allows for ultra-low latency when moving data between the I/O channels and the CPU.
The ADCs and DACs in the RT Box both feature 16 bit resolution at a maximum sample rate of 2 Msps. The inputs and outputs can be adjusted to common industrial voltage ranges. All I/Os are protected against ESD, short circuiting and accidentally applied overvoltages.
The digital I/Os are typically used for high-fidelity PWM capture and PWM generation, but can also provide general purpose I/O functionality. They are compatible with 5 V and 3.3 V signal levels.
The RT Box operates hand-in-hand with a host computer running PLECS Standalone and the PLECS Coder. The PLECS Coder translates a PLECS model into real-time capable C code to be compiled for running on the RT Box. The original PLECS model on the host computer can be connected to the simulation on the RT Box using an External Mode. This allows the user to visualize simulation results from the RT Box in the PLECS Scope and to tune parameters on the fly.
The supporting documents can be free downloaded by following link:
New Video on RT Box online